1. Field of the Invention
The present invention relates to an integrated circuit package.
2. Description of Related Art
Integrated circuits are typically enclosed by a package that is mounted to a printed circuit board. The package has a plurality of external contacts that are solder to the printed circuit board and dedicated to the various power, ground and signal pins of the integrated circuit. The contacts may be solder balls that are attached to external conductive lands of the package. Packages with external solder balls are typically referred to as ball grid array (BGA) packages.
The packages have internal routing layers which couple the external lands to internal bond fingers that are wire bonded to the surface pads of the integrated circuit. The internal routing typically contains separate layers for a ground bus, a power bus and a plurality of signal lines. The various layers are coupled to the external lands by vias that extend through the substrate.
Some highly functional integrated circuits such as microprocessors require different power voltage levels. For example, some devices require both 5.0 volt and 3.3 volt power. The package must have two different power planes to accommodate the different voltage levels. The extra power plane requires additional layers and fabrication steps that increase the cost of the package. The multiple power busses also require additional vias that also increase the cost of manufacturing the package. It would be desirable to provide an integrated circuit package that incorporates multiple power planes without increasing the number of layers and vias of the package.
It is desirable to mount capacitors to an integrated circuit package. The capacitors can either be mounted internally within the package or on the top surface of the package. Mounting the capacitors internally occupies valuable routing space. It is therefore desirable to attach the capacitors to the top surface of the package.
Many packages incorporate a thermally conductive heat slug to facilitate the removal of heat generated by the integrated circuit. The heat slugs are typically attached to the top surface of the package and occupy space that could be utilized for the capacitors. Additionally, the capacitors are mounted to conductive land strips which must be flat to insure a rugged solder joint between the strips and the capacitors. To insure flatness, it is desirable to form the lands in an area that does not have vias. Packages of the prior art require a via for each external land. Removing a via will therefore eliminate a land and may reduce the functionality of the package. The utilization of a heat slug and vias thus limit the space available for the capacitors. It would be desirable to provide an integrated circuit package that contains an optimum number of capacitors without degrading the thermal performance and number of lands on the package.
The present invention is an integrated circuit package. The package includes a substrate that has a first internal conductive bus and a second internal conductive bus that are dedicated to different power voltage levels. The busses are coupled to external lands located on a first surface of the package by vias that extend through the substrate. The vias also couple the lands to other internal busses and signal routing lines within the package. The first and second busses are located on a common layer of the substrate.
The package contains an integrated circuit which is mounted to a heat slug that is attached to a second surface of the package. The integrated circuit is coupled to bond fingers located on a shelf of the substrate. Some of the bond fingers are connected to the internal busses by conductive strips that wrap around the edges of the shelf.
Placing some of the busses in the same plane and coupling the busses to the bond fingers with conductive strips reduces the number of layers and vias required to construct the package. The reduction in layers and vias lowers the cost of producing the package. Some of the vias are connected to a whole group of external lands. Grouping the lands to a single via reduces the number of vias on the second surface of the package. The reduction in vias allows additional capacitors to be mounted to the second surface of the package.